power integrity , Chip-Package Co-Design, Physical Design, floorplanning, Bump Planning, Package Interface Design, Signal Integrity, EDA Tools, Package Design

routing, congestion analysis, IR drop, primetime, floorplanning, physical ECO implementation, physical optimization, Cadence Innovus, LVS, Power Planning, Physical Verification, antenna checks, Calibre, Physical Design, StarRC, ERC, Timing Closure, DRC, Placement, sign-off, RTL-to-GDSII, Synopsys ICC2

EM IR understanding and fixes, PV closure, Util area reduction experiments, Physical aware Synthesis using FC, ECO cycle, STA analysis, PnR-Floorplan Macro placement, Density Congestion Timing issues and fixes on lower tech nodes 5nm

Flows, Physical Design, verbal and presentation skills, Design Methodologies, debugging skills, sign-off tools

power integrity , Unix, Linux, Tcl, Python, routing, signoff, electromigration signoff, physical signoff flows, Placement, Extraction, floorplanning, CTS, EM IR analysis, static and dynamic IR-drop analysis, decoupling strategies, power grid architectures, Ansys RedHawk, Cadence Voltus