simvision , pipelining , Vcs, Verilog, Static Timing Analysis, Design Compiler, primetime, Xcelium, clock domain crossing, Waveform tools, VHDL, Genus, RTL design and simulation tools, Digital logic design concepts, Verdi, Synthesis tools, systemverilog, Axi, FPGA ASIC design flow, BUS Protocols, Fsms, APB, Modelsim, AHB, Low-power design techniques

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques