Shell, PERL, System Verilog, Python, Tcl, full-chip mixed-signal verification, Uvm, HDL synthesis, Analog design verification, Analog IC Circuit design

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

Low Power SoCs, Physical Verification, Physical Design, Timing Closure, Floor Planning, Dynamic IR Drop, Package Co-design, Place And Route, IO Planning, Clock Tree Synthesis, Power Grid Design