Jtag, MBIST, FastScan, DFT architecture, Scan Insertion, ATPG, Synopsys TetraMax, EDT, Scan Compression, Stuck-at, At-speed, TestKompress, Mentor Tessent

Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence

Scan, HDLs, MBIST, DFT architecture definition, Tempus, ATPG flow implementation, scripting skills in Perl, Genus, tessent DFT, JTAG boundary scan, Cadence digital implementation tools

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, timing fixes corrective actions for timing violations, ASIC DFT

Jtag, Perl, Tcl, Memory BIST, Fusion Compiler, ATPG, AI-assisted workflows, Genus, Scan insertion techniques, Primetime STA, Scan architecture

logic bist , DFT architecture, Functional BIST, Digital design flows, Scan compression, SoC MCU architecture, DFT protocols