Static timing analysis, Shell scripting, System Verilog, Test-bench components, Verification environment, Synthesis timing analysis, RTL linting, Uvm, Timing Closure, RDC techniques, Dft, Synthesis, FPGA kits, Verilog RTL design, Timing Constraints, Gate level verification, Simulation, Hardware Verification

pipelining , boundary scan , Pcie, Verilog, Python, Perl, Ethernet, Tcl, cdc, ARM-based SoC integration, Simulation, Scan, UVM-based testing, UPF, Dft, SERDES, EDA Tools, RTL SystemVerilog, low-power techniques, Synthesis, digital design fundamentals, MBIST, AMBA protocols, Axi, Fsms, APB, LINT, synchronous design, CXL, AHB