routing, Perl, Python, Tcl, Sta, CTS, primetime, PrimeTime-SI, floorplanning, physical signoff, Asic Physical Design, advanced-node SoCs, SDC, Eco, MMMC, Timing Constraints, Timing Closure, Placement, complex hierarchical designs, full-chip implementation

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

EM IR understanding and fixes, PV closure, Util area reduction experiments, Physical aware Synthesis using FC, ECO cycle, STA analysis, PnR-Floorplan Macro placement, Density Congestion Timing issues and fixes on lower tech nodes 5nm