Shell, Verilog, Unix, C, Python, Perl, Linux, Uvm, systemverilog

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Pcie, Verilog, Ethernet, Prototyping, Python, Scripting, Tcl, UCIe chiplet interconnects, AI tools, cdc, area optimization, Emulation, systemverilog, high-speed IO protocols, Rtl Design, formal verification, RDC, LINT, Timing Closure, silicon bring-up, CXL, micro-architecture, power efficiency

DDR, Pcie, Perl, Ethernet, Python, Design Verification, Uvm, emulation environments, RTL Verilog, HBM, SoC IP, high-speed protocols, AI ML SoCs

code coverage , closure , automation, Ovm, Tcl Scripting, Verilog, Perl, SDF, GLS, Uvm, RTL, SV, Specman, test-bench development, HVL, assertions development, eRM methodology, formal verification, constraint randomization

Tcl, FPGA Design, System Verilog, C, Python, Unix Shell Script, Perl, Vcs, Synthesis, RTL validation, LINT, Synopsys simulators

automation, Scripting, Static Timing Analysis, Python, AHB, Synthesis, LINT, EDA Tools, frontend flows, memory interfaces, standard interface protocols, SoC-level integration, cdc, Memory Controller IPs, Rtl Design, Safety Security and Debug architectures, Interconnect Fabrics, formal verification techniques, static dynamic power checks, Axi, Dft, ARM Cores