Design-for-Debug (DFD) and Verification Debug, Verilog, Usb, Pcie, UVM-based Verification Environment Development, Verification Planning Execution, SoC Subsystem Verification, Testbench Development, Interconnect Verification, systemverilog, Functional Coverage, UFS, Axi, Assertions SVA, EMAC Ethernet, Coverage-driven Verification, AHB, AMBA ATB Protocols

Uart, Usb, Tcl, Ethernet, Perl, Spi, I2c, Shell Scripting, Python, DDR, AHB, UCIe, Siemens QuestaSim, Functional Coverage, systemverilog, MIPI, CXL, DVE, APB, Axi, Cadence Xcelium, Uvm, Constrained Random Verification, Scoreboards, Verdi, Functional Checkers, Synopsys VCS

Usb, Vcs, DDR, Pcie, Perl, Ethernet, Shell scripting, Python, Tcl, Xcelium, Uvm, systemverilog, Questa

Pcie, Ovm, Scripting, System Verilog, Ethernet, Uvm, HBM2, HBM3, Memory protocols, GDDRx, SVA, AHB, LPDDR4, AMBA standards, APB, High speed SerDes, Axi

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

clocking , Verilog, System Verilog, SOC Emulation, SOC boot flow, Power management flows, Synthesis, PNR, FPGA based prototyping platforms, Low Power Verification, System Verilog Assertions, RTL GLS level simulations, Platform bring up in Emulators or Silicon, Emulation platforms, Functional Verification, Timing Analysis

ARM M-series core operations, DMA interrupt handling, Debugging using disassembly and Tarmac for ARM cores, C code for ARM processors, UVM testbench development, Cache and interconnect, Cadence simulators and SimVision, Cadence and Synopsys VIPs, AHB and APB interface protocols