Perl, Verilog, Python, Uvm, systemverilog

bandwidth management , Universal Verification Methodology (UVM), Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, revision control systems, packet processing, AI ML Accelerators, constrained-random verification environments, Verification

Jenkins), Issue-tracking (e.g., Jira), Continuous integration (e.g., Simulation and analysis environments (e.g., Simscope), SystemVerilog Assertions, Uvm, systemverilog, Synopsys verification suites

arm architecture , C, C++, Encryption, Pcie, ACE lite or CHI bus protocols, Coherent and non-coherent fabric IPs and protocols, SoC Verification, DMA, PCIe Controller PHY IPs and protocols, CXL, decompression, decryption, DDR protocols, Compression, Memory Controller PHY IPs, Data accelerator verification

Verilog, formal verification, VHDL, Chisel, JasperGold, VC Formal, Object-oriented Programming, Formal Abstraction Techniques, systemverilog

code coverage , MATLAB, Functional Coverage, large-scale regression debugging, System Verilog UVM, directed testing, constrained-random verification, Fixed-Point Designer, C reference models, DSP and arithmetic data paths, model-based verification, RAL

Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Debugging, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso, test bench development, verification IP, object-oriented programming, Simulation, behavioral modelling, mixed signal verification environment, verification plans, analog blocks

C, C++, Ci, Git, Python, protocol analyzers, error injection, Emulation, fault modeling, agile development practices, UCIe, Axi, Keysight, Teledyne LeCroy, DMA, silicon debug tools, ASIC front-end architecture