Silicon Validation, control-loop stability, data converters, signal-conditioning blocks, Sensors, analog feedback loops, charge pumps, mixed-signal IC development, switching converters, Verification, power management, Analog Design, LDOs

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification