static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

Python, Xcelium, SystemVerilog-RNM, Uvm, Spectre, Synopsys VCS, Cadence Virtuoso, Ansys Lumerical, Verilog-AMS, analog mixed signal verification, Synopsys OptoCompiler, Skill, FineSim, optical simulation tools

synopsys primetime , Shell Scripting, Perl, Python, Tcl, Tempus, SI OCV AOCV POCV CDC, Setup Hold Analysis, StarRC, Timing Exceptions, Low-Power Timing Methodologies, Timing Convergence Techniques, Timing Signoff

Validation Testing, Data acquisition systems, Fmea, Dfmea, Simulation Design

reactor design , Automation, Solidworks, ANSYS, Heat Mass Transfer, Pressure Vessel Engineering, Production Planning, Autocad, Aspen Plus, reaction engineering, Mechanical Design, Lean Manufacturing, Aspen Hysys, CFD Analysis, Process Simulation

Ethernet, Pcie, Synopsys, Uvm, advanced verification methodologies, systemverilog, Mentor, Cadence, PAM4, Register modeling, D2D, protocol VIP integration, Avery, PAM2