Jtag, MBIST, FastScan, DFT architecture, Scan Insertion, ATPG, Synopsys TetraMax, EDT, Scan Compression, Stuck-at, At-speed, TestKompress, Mentor Tessent

boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis

Tempus, HDLs, MBIST, DFT architecture definition, ATPG flow implementation, JTAG boundary scan insertion, Pattern Simulation, Scan, Genus, Cadence digital implementation tools

Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence