Jtag, Perl, Tcl Scripting, coverage improvement techniques, Test structures for DFT IP Integration, tile level and chip level STA flows, ATPG Fault models, Scan insertion techniques, Memory BIST generation, MBIST, Post-Si ramp up and debug on ATE, Test mode timing constraints, Industry standard Tools for Scan insertion, cross domain knowledge, ATPG, Scan, gate level simulations, test point insertion