Static timing analysis, Soc, Verilog, quality assurance, AHB, Timing Constraints, LINT, systemverilog, Design Verification, cdc, Logic Synthesis, ASIC, physical implementation, AXI Stream, low power design, formal equivalence, APB, Dft, power analysis

Yocto, Robot Framework, Shell scripting, Python, BSP customization, Android build systems, Linux driver experience, HLOS internals, Networking fundamentals

synopsys tools , PERL, Python, Tcl, Sta, SoC Synthesis, Low power CDC, Verification, UPF, Synthesis, PNR, LINT tools, Digital Implementation, SOC design, Front End Signoff, Analog Block Integration, Low Power Implementation, SoC Integration

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

Data Analytics, Machine Learning, Nvme, Windows, Pcie, Linux, Python, AI tools, Generative AI, protocol analyzers, debugging NVMe SAS protocol issues, Storage Subsystems, test automation framework development, storage validation platforms, SSD architecture, validation plans, NAND Flash technologies

liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL