Electromigration (EM), Perl, Automation Frameworks, Python, Tcl, Tape-out experience with TSMC N3, primetime, Fusion Compiler, IC Compiler II, Synopsys DSO.ai, CPU micro-architecture, Cerebrus, Timing Closure, Standard Cell SRAM library architectures, Synopsys Fusion Design Platform, Physical Design and Methodology, Flows-as-Code, Sub-3nm device physics, Dynamic IR drop, Crosstalk challenges

power integrity , static timing analysis, Pvs, Python, Tcl, place-and-route, primetime, floorplanning, ICC2, Cadence Innovus, Synopsys Fusion Compiler, advanced-packaging, Physical Verification, Calibre, StarRC, Timing Closure

Power gating and retention strategies, Signal Integrity Analysis, Power Planning, ASIC SoC physical design, Leakage optimization and dynamic power reduction, UPF CPF-based low-power implementation flows, Timing Closure, Physical Verification and Signoff, Advanced low-power architectures, Clock gating methodologies, Adaptive power management techniques, Floor planning and Partitioning, Power-aware physical design and implementation closure, Placement and Optimization, Routing and Congestion Analysis

Java, Paas, Golang, Technical Leadership, Saas, Iaas, Gcp, Javascript, Python, AWS, data streaming platforms, large scale distributed systems, architectural oversight, event-driven architecture

Scripting, EMIR Signoff flow, In-rush current profiles, Data Analysis, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

saml 2.0 , Python, Kerberos, PowerShell, Ldap, PAM, Apis, OAuth 2.0, Pluggable Authentication Modules for Linux, x.509, infrastructure-as-code, certificate-based authentication, LDAPS, Oracle Unified Directory OUD, SSH key-based authentication, OpenID Connect OIDC, Unix authentication, Active Directory, Azure AD B2C, Entra ID, RADIUS, SCIM

routing, Perl, Python, Tcl, Sta, CTS, primetime, PrimeTime-SI, floorplanning, physical signoff, Asic Physical Design, advanced-node SoCs, SDC, Eco, MMMC, Timing Constraints, Timing Closure, Placement, complex hierarchical designs, full-chip implementation

Jenkins, Devops, Git, Docker, Kubernetes, Python, AgenticAI frameworks, R, AI ML engineering, CI CD tools

static timing analysis, Floor Planning, Synthesis, Makefile scripting, physical design CAD flow, physical design verification, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus

Git, Visual Studio, Agile Development, Python, Board-level debugging, RapiTest, Hardware software integration, Wind River VxWorks