Debugging, Scripting, RTL Coding, ECO flows, LINT, formal equivalence, cdc

Python, FineSim, Synopsys VCS, Xcelium, Skill, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL

Silicon Validation, control-loop stability, data converters, signal-conditioning blocks, Sensors, analog feedback loops, charge pumps, mixed-signal IC development, switching converters, Verification, power management, Analog Design, LDOs