Perl, Debugging, Shell scripting, Python, Tcl, Uvm, Mixed-Signal Verification, systemverilog

Perl, Ovm, Python, Axi, APB, AMBA protocols, Uvm, AHB, systemverilog

Pcie, Perl, Python, System Verilog, Tcl, CHI, SMMU, assertion-based verification, Uvm, UPF, Coresight, Axi, formal verification, power-aware verification, coverage-driven testing, CXL, SVA

Kibana, Java, Kafka, Spring Boot, Grafana, Redis, Microservices, Elasticsearch, Nosql, Git, RDBMS, Docker, Reactjs, Postgres, Oracle, Kubernetes, Python, Event-driven architecture, GraphDB, Github Actions, Time-series DBs, Workflow automation

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Revision control systems, Verification testbenches, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors