Power distribution networks, Layout verification tools and methodologies, Signal integrity considerations, Analog Layout Design, Analog circuit design principles

redhawk , Shell, PERL, Verilog, Tcl, place and route methodologies, low power physical design flows and methodologies, Fusion Compiler, physical implementation and analysis tools, timing and signal integrity analysis, Innovus, Calibre, VHDL, power integrity and reliability analysis, power grid planning and implementation, Starrcxt, timing optimization and timing closure, placement and optimization, metal-only ECO implementation, floorplan exploration and optimization, Clock Tree Synthesis

Dac, ADC, CTS routing, Comparator, CMOS, Pll, Physical Verification, Bi-CMOS, Differential Amplifier, AMS IP integration, LDO, Charge Pump, PNR flow, PHY, SERDES, Custom Layout, SOI, Analog Mixed Signal Layout design, FinFET processes, Bandgap Ref Generators, Current Mirrors, Timing Closure, HDMI, Routing Congestion

Calibre, Mixed Signal Layout, Physical Verification, Analog Layout, DRC, Custom Layout, virtuoso, LVS, Chip Level Integration, CAD Tools, Layout Electrical Parameters

Routing, Mixed-Signal Layout Design, Mentor Siemens Calibre, Device-Level Layout, floorplanning, Cadence Virtuoso, Parasitic Extraction

FinFET technologies, Calibre, Mixed-Signal Layout, pegasus, DRC, Physical Verification, LVS, Analog Layout Design, Cadence Virtuoso

manufacturing processes , assembly processes , product life cycle , Plm, project management, tolerance stack-up analysis, materials selection, production costing, product design development, CAD Tools, quality value engineering, supply chain optimization, Creo, industrial costing, Pdm