Uart, Spi, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Microsemi FPGAs, Uvm, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Perl, Python, System Verilog, Building test benches from scratch, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS

System Verilog, Gate Level Simulations, Building test benches, ASIC verification using UVM, formal verification

protocol stack , LTSSM, integrating PCIe into large SoCs, architecture and verification, UCIe architecture, PCIe Gen4 5 6, SerDes architecture, root complex endpoint switch architectures, Chiplet ecosystem

Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi

data link layer , CDC synchronizers, Virtual Channels, PCIe architecture, clock crossing, PCIe compliance testing, SystemVerilog RTL, flow control, PnR constraints, Transaction Layer, reset sequencing, async FIFO, multi-clock-domain design, TLP structure, Physical Layer, PCI-SIG certification process, PCIe PHY-MAC interface protocols, error handling, CXL 1.1 2.0 or 3.0 protocol knowledge, PCIe power management

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

flash translation layer , Embedded Firmware, Test Plans, Linux Operating System, Python, AI tools, Back End NAND Media management, Lecroy JDSU analyzers, SSD Product Validation, Automated test environment, NVMe Protocol, PCIe-CV test suites, IO workloads