C, Shell, Verilog, Python, Systemc, Test Planning, Tcl, power-aware verification using UPF, systemverilog, constrained-random verification, transaction-level modeling, formal verification, assertions, UVM-based testbench development, NoC bus and interconnect verification

liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL

test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Revision control systems, Verification testbenches, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

liberty , Scripting, Tcl, python, Pcie, DDR, IO standards, bump map pattern definition, pad ring planning, RTL, Isp, EDA Tools, IO cell placement, PHY-level IO interfaces, Orbit IO, CXL, IO library cells, flow automation, lef, SERDES