hardware engineering , Clock Tree Synthesis (CTS), Unix, Perl, Linux, Low power verification, floorplanning, Placement, power analysis, PNR implementation, CTS optimization, Optical systems, Equipment and packaging test systems, DSP systems

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

EM), Power integrity analysis (IR drop, Antenna), Physical verification (DRC, Static Timing Analysis (STA), Routing, Mentor Calibre, VLSI design principles, LVS, Physical design methodologies, floorplanning, Cadence Innovus, Synopsys Fusion Compiler, Semiconductor physics, Timing closure techniques, Design Verification, RTL synthesis, Placement, Deep sub-micron process technologies

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation