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ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Cisco DevNet

10-12 yrs

Bengaluru, India

Skills:

Perl, Python, System Verilog, Building test benches from scratch, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS

Early Applicant

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Cisco Home

10-12 yrs

Bengaluru, India

Skills:

Perl, Python, System Verilog, Test benches, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS

Early Applicant

FPGA Design Technical Leader- Ethernet,PCIe, System Verilog, Xilinx- 12+ Years

CISCO Credit

12-14 yrs

Bengaluru, India

Skills:

Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Microsemi FPGAs, Uvm, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Early Applicant