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FPGA Design Technical Leader

Cisco DevNet

15-17 yrs

Bengaluru, India

Skills:

memory controllers , Uart, Spi, FPGA Design, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Microsemi FPGAs, Uvm, quartus, Axi, VHDL, Vivado, VMM, RTL Coding, Libero

Early Applicant

FPGA Design Technical Leader

Cisco Live

15-17 yrs

Bengaluru, India

Skills:

Unix, Uart, Spi, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Otn, Microsemi FPGAs, Uvm, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Early Applicant

IP RTL Design Leader

Tenstorrent

15-17 yrs

Bengaluru, India

Skills:

Usb, DDR, Pcie, Verilog, Python, Tcl, Uvm, systemverilog, Rtl Design, Axi, formal verification, APB, AHB

Early Applicant

ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

Cisco Home

12-14 yrs

Bengaluru, India

Skills:

Vcs, System Verilog, ATE patterns, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Scan and BIST architectures, Gate level simulation debugging

Early Applicant

FPGA Design Technical Leader- Ethernet,PCIe, System Verilog, Xilinx- 12+ Years

CISCO Credit

12-14 yrs

Bengaluru, India

Skills:

Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Microsemi FPGAs, Uvm, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Early Applicant