Clarity, PCIe Gen4, MIPI D-PHY, PCIe Gen5, Cadence Sigrity, TDR, USB 3.x, VNA, SIwave, Keysight ADS, Ansys HFSS, DDR5, LPDDR, DDR4, C-PHY, high-bandwidth oscilloscopes

Networking, Jtag, Usb, Nvme, Storage, Graphics and Display, Logic Analyzers, Post Silicon Validation, Oscilloscopes, Memory Training, Crash Dump Analysis, Python Automation Frameworks, Platform Security, Silicon-to-System Interactions, PCIe Gen4, Debug Tools, Platform Debug, Customer Engagement, Firmware Traces, Debug Methodologies, RAS Technologies, DDR5, DDR4, Protocol Analyzers

arm architecture , C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, pre-silicon SoC verification, performance verification, PCIe CXL Controller PHY IPs and protocols, DDR protocols, Memory Controller PHY IPs