rc extraction , Python Scripting, hierarchical design methodologies, IR EM Voltus, DRC LVS Calibre flows, power intent, Cadence Innovus PNR tool, STA PrimeTime, clock mesh tree design

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, LVS, Voltus, MMMC, Timing Closure, DRC, EM IR analysis, full-chip implementation

Formal verification (LEC), Static Timing Analysis (STA), Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

power integrity , Power Delivery Network (PDN) optimization, Signal Integrity (SI), Clock Tree Synthesis (CTS), Electromigration (EM), Static Timing Analysis (STA), floorplanning, UPF, Routing Optimization, IR Drop, Physical Verification, Placement, ASIC SoC Physical Design, CPF, multi-voltage design techniques

static timing analysis, Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, equivalence checking, Physical Design, CDC linting

synopsys primetime , Perl, Python, Tcl, Unified Power Format UPF, Tweaker, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass Constraints, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, PrimeClosure, Cadence Tempus, Synopsys Formality, Timing Closure ECO Cadence Tempus

Design for Test (DFT), SDC (Synopsys Design Constraints), boundary scan , Static Timing Analysis (STA), scan compression, scan architecture, Memory BIST, ATPG, Siemens EDA Tessent tools, Timing Closure, synthesis and scan insertion tools

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation