static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols

Verilog, formal verification, VHDL, Chisel, JasperGold, VC Formal, Object-oriented Programming, Formal Abstraction Techniques, systemverilog

Logic Equivalence Checking (LEC), Static Timing Analysis (STA), Python, Tcl, RTL Synthesis, Low Power UPF IEEE 1801, primetime, Fishtail

Unix, Shell, Linux, Verilog, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, LINT, Low Power

Routers, DDR memory subsystem design and optimization, High Speed PCB design validation, Manufacturing support and product sustainment, Signal integrity SI and Power Integrity PI analysis and review, Timing synchronization and clock distribution systems, Power distribution network PDN architecture and design, 100G Ethernet systems, PCIe PAM4 based SerDes technology, High-speed Ethernet switches, Hardware debugging and root-cause analysis

Tcl, Python, Perl, Innovus, Physical Formal Verification, Cross-Functional Collaboration, LEC, primetime, EDA Tools, Fusion Compiler, Calibre, Red Hawk, Tempus, Timing Closure STA, RTL-to-GDSII Execution, Programming Scripting, VCLP, PPA Optimization