bist , Jtag, Perl, Verilog, Python, Tcl, PrimeTime PT, Synopsys Design Compiler DC, Formality, Static Timing Analysis STA, ASIC Digital IC Design, SDC, Dft, formal verification, ATPG, Timing ECO, Timing Closure, Scan, Logic Synthesis

Critical clean utility systems, Engineering change controls, Root-cause analysis, Troubleshooting