Shell, Perl, Python, Tcl, coverage-driven methodologies, Uvm, systemverilog, SVA, constrained-random verification

Integration, System Verilog, Test Planning, testbench stimulus agent monitor checker development, Asic Design Verification, coverage driven constraint random verification, Uvm, Validation, c based reference model

Perl, Shell Scripting, Python, Tcl, Formal Verification Techniques, Mixed-Signal Verification, systemverilog

Fpga, Vcs, Pcie, Ethernet, Xcelium, Emulation, Uvm, systemverilog, Dft, Questa, DDR5, DDR4

Usb, Nvme, Pcie, Python Programming, C Programming, Protocol analyzers, Logic Analyzers, USD, Oscilloscopes, Sd, Flash Memory, Function Generators

UVM (Universal Verification Methodology), Tcl, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, C/C++, System Verilog Assertions, Design Verification infrastructure

Verilog, Python, Synopsys, low power design techniques, performance modeling tools, bus architectures, Cadence Tools, accelerators, memory hierarchies, arithmetic units

Assertion-Based Verification (SVA), Connectivity Verification, Security Checks, Protocol Compliance Verification, formal verification, Deadlock Analysis, Formal Coverage Analysis, Property Verification, Uvm