Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

DDR, Shell, Perl, Pcie, Python, systemverilog, JESD204B, Uvm, UPF, GLS, MIPI, Dft, USB3

Verilog, SOC boot flow, systemverilog, Low Power Verification, System Verilog Assertions, RTL GLS level simulations, power management flows, UVM OVM based Methodology Development, coverage report generation, clocking and platform bring up in Emulators or Silicon

Noc, Usb, DDR, Pcie, Perl, Ethernet, Python, Tcl, SVA, Functional Coverage, Uvm, systemverilog, DDR5, LPDDR, DDR4

Tcl, Shell scripting, Vcs, Usb, Ethernet, Python, Pcie, Perl, DDR, Questa, Uvm, systemverilog, Xcelium

Jtag, Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Trace triggers, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, Asic Design Verification, Crash flow, Power aware simulations, monitors, Validation, AHB, Scandump

C, Tcl, Python, Perl, AHB, GLS, SystemRDL, Uvm, UPF, systemverilog, RAL, IP-XACT, Tk, APB, Axi

ARM M-series core operations, Cadence simulators and SimVision, C code for ARM processors, AHB and APB interface protocols, Cadence and Synopsys VIPs, Debugging using disassembly and Tarmac for ARM cores, UVM testbench development