redhawk , Perl, Tcl, Dc, floor-planning, layout activities, Pt, automation flows, Quantus, Tempus, Physical Verification, Mentor EDA tools, Voltus, timing and functional ECO, Innovus, Star-RCXT, STA closure, Genus, partitioning, Placement, P&R flows, Clock Tree Synthesis, PrimeRail

routing, Debugging, STA timing closure, Optimization, EM IR analysis and closure, Full-Chip Physical Design, Cadence Innovus, Physical Verification, Clock Tree Synthesis, Problem-solving

Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

hardware engineering , Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Clock Tree Synthesis (CTS), Physical Design Planning, Placement, Floor Planning

Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, RTL-to-GDSII flow, Synthesis, Physical Design, Placement, Si, DRC