boundary scan , Jtag, Scripting, Tcl, multi-clock domain designs, DFT signoff, scan architecture, MBIST, DFT architecture, Timing Constraints, ATPG, clocking architectures, silicon bring-up, LBIST, manufacturing test flows, compression methodologies

Formal verification (LEC), Static Timing Analysis (STA), Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress

synopsys primetime , Perl, Python, Tcl, Unified Power Format UPF, Tweaker, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass Constraints, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, PrimeClosure, Cadence Tempus, Synopsys Formality, Timing Closure ECO Cadence Tempus

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, LVS, Voltus, MMMC, Timing Closure, DRC, EM IR analysis, full-chip implementation

Perl scripting, Test Strategy, Python, Tcl, Synopsys DFTMAX, Silicon Bring-up, MBIST, SoC Tape-outs, Siemens Tessent, ATPG, Cadence Modus, Scan Compression, IEEE 1149.1, Hierarchical DFT, LBIST, TestMAX, DFT Architecture