Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Routing, Perl, Shell scripting, Python, Tcl, floorplanning, Cadence Innovus, Power Planning, Calibre, Placement, Timing Closure, Physical Design implementation, Synopsys Fusion Compiler ICC2

Computer Architecture, Logic Design, Perl, Verilog, Python, LINT, high performance computing, Digital Signal Processing Techniques, HLS, Synthesis, VHDL, Physical Design tools

Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Unix, Ilm, Linux, Tcl, Python Scripting, QRC models, back-annotation, Multi-Vt, SPEF correlation, Cadence Tempus, Tempus SI, voltage island timing, ETM, OCV, Timing ECO methodology, Advanced nodes 12nm or below, STA fundamentals, glitch, CTS timing implications, MMMC, SDC expertise, crosstalk, Cadence Conformal ECO, Physical-aware Tempus experience, POCV, Innovus–Tempus in-design timing, AOCV

Routing, Python, Tcl, Sta, CTS, Signoff, floorplanning, EM Noise, LVS, Power Planning, IR Drop, Physical Verification, Eco, Physical Design, Placement, Timing Closure, Si, DRC

Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, Synopsys, ICV

Place and Route (P&R), Python, Tcl, RTL-to-GDSII flow, Synthesis, Physical Design, Genus, Post-route signoff, ICC2, Synopsys Fusion Compiler, Cadence Innovus