Git, Perl, Python, System Verilog, Tcl, Synopsys Design Compiler, primetime, Fusion Compiler, ICC2, Formality, LEC, UPF, Innovus, VHDL, Linux Shell, spyglass, UNIX/Linux environments

Python Scripting, Tcl Scripting, Innovus ICC2, Fusion Compiler, Experience in advanced nodes 7nm and below

DFT DRC, DFT architecture, Scan Insertion, MBIST Implementation, SoC-level DFT Integration, ATPG, Fault Coverage Analysis, Scan Compression, JTAG IEEE 1149.1, Debug

Perl, Python, Tcl, LVS, Siemens Calibre, PERC, TVF, Calibre Interactive, Cadence Pegasus, CalibreDRV, Calibre DesignRev scripting, DRC, Tk, Cadence Virtuoso, SVRF

Out of Order Super Scalar Multi-Threaded Core Architecture, Processor Core silicon bring up, RTL design with Verilog or VHDL, High frequency instruction pipeline designs

Real-Time Operating Systems (RTOS), C, C++, Soc, MATLAB, Git, Uml, Verilog, VxWorks, Coverity, Arm, Simulink, VHDL, Xilinx

Doors, Vcs, Jira, MATLAB, Jama, System Verilog, Polarion, DO-254, QuestaSim, Uvm, Code coverage assertions, VHDL, UVMF, Aldec