Design Engineer II

Fpga, C, Pcie, Ethernet, Python, Test result analysis, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, Peripheral chips, High speed SERDES, High speed interface design techniques, UCIe, Debug skills, Lab automation scripts, Schematic and layout level, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Post-Silicon PHY Systems Interop and Compliance testing, Signal and Power integrity checks

Fpga, C, Pcie, Ethernet, Python, Test result analysis, Calibration compliance lab suites, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, High speed SERDES, UCIe, Debug skills, Lab automation scripts, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Signal and Power integrity checks, Post-Silicon PHY Systems Interop and Compliance testing

redhawk , Shell, PERL, Verilog, Tcl, place and route methodologies, low power physical design flows and methodologies, Fusion Compiler, physical implementation and analysis tools, timing and signal integrity analysis, Innovus, Calibre, VHDL, power integrity and reliability analysis, power grid planning and implementation, Starrcxt, timing optimization and timing closure, placement and optimization, metal-only ECO implementation, floorplan exploration and optimization, Clock Tree Synthesis