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Design Verification Engineer
ALTEN Calsoft Labs

Design Verification Engineer

ALTEN Calsoft Labs
2-4 Years
Not Disclosed
Early Applicant
  • Posted 2 months ago
  • Be among the first 40 applicants

Job Description

Job Title: Design Verification Engineer

Exp Level:2+yrs

Location: Bangalore/Hyderabad

Job Description:

Responsible for ensuring functional correctness of ASIC/SoC designs.

Key Task: Develop and execute verification plans for complex digital designs.

Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures.

Coverage: Achieve functional and code coverage targets through constrained random and directed testing.

Collaboration: Work with RTL designers to identify and resolve design bugs.

Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug.

Protocols: Verify IP/SoC-level designs for common protocols (AXI, APB, PCIe, DDR, etc.).

Automation: Develop scripts (Python/Perl/TCL) to improve verification efficiency.

Documentation: Maintain verification reports and review results with stakeholders.

Compliance: Ensure adherence to project timelines and quality standards.

Interested can share CV to [Confidential Information]

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Engineering
Employment Type:
Full time

Key Skills

Uvm

Verdi

Questa
systemverilog
Perl
Vcs
Python
Tcl

About Company

Last Updated: 26-10-2026 08:03:00 PM

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