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Mirafra Technologies hiring for a Design Verification Engineer with 5+Yrs Experience.
Location-Bangalore/Hyderabad
Qualification-BE/B Tech/M Tech
1. Must Have: SoC or IP Verification
2. Experience Languages: System Verilog
3. Methodologies: OVM/UVM/VMM
4. Protocols: PCIE/DDR/Ethernet/UFS/CHI
5. Processor/ARM Based SoC Verification experience
6. Candidate must have expertise in System Verilog.
7. Experience in ARM base SoC Verification
8. Strong Analytical skills are desirable if having worked
Kalpana Bhatia
TA-Lead-Mirafra
[Confidential Information]
Job ID: 147210185
Skills:
Unix, Shell, C, Perl, Linux, Verilog, Python, Uvm, systemverilog
Skills:
Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification
Skills:
code coverage , Fpga, Ovm, Test Cases, Hdl, Shell, Pcie, Verilog, Debugging, System Verilog, Python, Perl, Pci, Sta, test benches, RTL, Uvm, DDR PHY, Ethernet MAC, VHDL, ASIC, RTL top level integration, Functional coverage, Frontend Design, Logic Synthesis, HVL
Skills:
Verilog, VMM, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, systemverilog
Skills:
C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, functional and code coverage closure
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