Lead Design Verification Engineer
Lead Design Verification Engineer
leadsoc technologies pvt ltd- Posted 11 days ago
- Be among the first 10 applicants
Job Description
Lead Design Verification Engineer – PCIe / Ethernet
Location: Bengaluru
Experience: 6–12 Years
Role Overview
We are looking for a Lead Design Verification Engineer with strong hands-on expertise in SystemVerilog, UVM, PCIe and Ethernet to drive IP and SoC-level verification for complex, high-performance designs.
Key Responsibilities
- Lead IP and SoC-level verification for complex ASIC designs.
- Develop scalable SystemVerilog/UVM-based verification environments.
- Define verification strategy, test plans, coverage goals and sign-off criteria.
- Drive functional verification of PCIe and Ethernet interfaces/protocols.
- Develop constrained-random tests, sequences, scoreboards, monitors and functional coverage.
- Debug complex simulation failures using VCS/Verdi or equivalent tools.
- Drive functional and code coverage closure and verification sign-off.
- Work closely with RTL, Architecture, Firmware, DFT and Physical Design teams.
- Develop reusable verification components and improve verification methodologies.
- Mentor junior engineers and provide technical leadership.
Required Skills
- 6–12 years of ASIC/SoC Design Verification experience.
- Strong hands-on expertise in SystemVerilog and UVM.
- Strong experience in PCIe and Ethernet protocol verification.
- Experience with IP, subsystem and SoC-level verification.
- Good understanding of high-speed protocols, SoC architecture and IP integration.
- Experience with VCS/Verdi, assertions and functional coverage.
- Strong debugging and scripting skills using Python/Perl/Tcl.
- Experience in verification planning, regression and sign-off.
- Strong communication and technical leadership skills.
More Info
Job Type:
Industry:
Function:
Employment Type:
About Company
Skills:
Shell, Perl, Python, Tcl, Test Cases, Cadence Xcelium, Mentor QuestaSim, Synopsys VCS, Constrained Random Verification, Functional Verification, PCI Express PCIe protocol, ASIC SoC Design Verification, Functional Coverage Models, Verification Plans, Waveform analysis, Assertion-Based Verification SVA, Simulation Tools, SystemVerilog UVM, Testbenches, Assertions
Skills:
Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB
Skills:
Jtag, Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Trace triggers, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, Asic Design Verification, Crash flow, Power aware simulations, monitors, Validation, AHB, Scandump
Skills:
code coverage , JIRA, Pcie, Shell scripting, Python, Arm Cortex, C++, Git, Perl, Ethernet, Tcl, Uvm, transaction-level modelling, constrained-random verification, SERDES, Cadence vManager, functional coverage, verification methodologies, O-RAN, gate-level simulation, systemverilog, AMBA, Axi, hardware software co-verification, AHB
Skills:
Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model