Principal Engineer Design

Debugging, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, RTL changes for DFT, Zero delay and timing simulations, Post silicon bring up, Test architecture definition, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks

Debugging, Clp, Silicon Validation, Dft, Scan Insertion, ATPG, Rtl Design, Timing Closure, LEC, IEEE 1500

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Verilog, Computer Architecture, Subsystem hardening, Synthesis, object-oriented programming, floorplanning, Place And Route, DFT insertion, digital logic, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis

Jtag, System Verilog, Static timing analysis, DFT techniques, IEEE 1500 Standard, Commercial test generation tools, Logic diagnosis, Yield learning, Synopsys DFT Max, Tetramax tools, Verification UVM methodology, Mentor Tessent, IEEE 1687 standard, ATPG test pattern translation, ATPG tools, Scan insertion tools, Chip design Verilog, MBIST, Familiarity with ATE, Scripting Perl, Scan compression, Test compression software, Gate-level simulations, LBIST