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We HCL are seeking a highly motivated RTL Design Engineer with 7-12 years of experience to join our growing team. You will play a vital role in the design and development of complex digital logic for next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in RTL design methodologies and verification.
Responsibilities:
Qualifications:
Benefits:
Job ID: 145173667
Skills:
Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP
Skills:
Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA
Skills:
Python Scripting, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools
Skills:
Perl, Verilog, Shell Scripting, LINT, cdc, RTL Quality Checks, Micro Architecture Definition, Connectivity, SOC design, VCLP
Skills:
LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies
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