Senior Design Verification Engineer
Search Jobs
Search by job, company or skills
Search by job, company or skills
Job Opening: SoC Design Verification Engineer (IP Verification)
Experience: 10+ Years
We are seeking a highly skilled SoC Design Verification Engineer with strong expertise in IP and Sub-system level verification using SystemVerilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex SoC designs.
Key Responsibilities & Requirements:
Job ID: 144750917
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
Fpga, Perl, Python, object-oriented design, RTL, test plan development, emulation platforms, Uvm, systemverilog, automation scripts
Skills:
Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
