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Job Title: Senior Verification Designer
Experience: 5+ Years
Location: Remote
Overview
Seeking experienced verification engineers to work on advanced AI connectivity and high-performance networking architectures.
Responsibilities:
Own verification strategy and execution for SoCs/IPs (Switches, NICs)
Build block and system-level verification environments
Develop UVM/SystemVerilog testbenches, checkers, and coverage
Drive coverage closure and signoff
Collaborate with RTL, architecture, and software teams
Contribute to verification methodology and infrastructure
Requirements
5+ years in ASIC/FPGA verification (SystemVerilog, UVM)
Strong experience in networking architectures (Switches, NICs, SmartNICs)
Knowledge of Packet processing, RDMA, Ethernet, PCIe, MAC
Proven experience with high-performance systems
Formal, emulation, or FPGA experience is a plus
B.Tech/M.Tech/PhD in relevant field
Job ID: 148384647
Skills:
Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm
Skills:
Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification
Skills:
Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog
Skills:
Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB
Skills:
Python, Systemc, MDV, simulation scripts, hybrid testbenches, regression systems, verification execution, Uvm, systemverilog, testbenches, CDV, coverage models
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