SENIOR ENGINEER, ASIC TEST

About the Role
We are looking for a passionate and innovative ATE Test Engineer to design and deliver cutting-edge test solutions for HBM-DRAM devices using modern advanced ATE platforms. In this role, you will lead the development and implementation of test plans, ATE test programs, silicon validation, and test methodologies, while driving multi-site hardware design and development, product characterization, and high-volume production support. Success in this position requires a forward-thinking mindset and the ability to apply the right technologies to meet evolving challenges.

Key Responsibilities

• Develop and implement robust test strategies, plans, and ATE programs for HBM-DRAM devices.

• Drive silicon validation, characterization, and yield improvement initiatives.

• Design and debug test hardware, including schematic capture and PCB layout.

• Collaborate cross-functionally to ensure seamless integration of test solutions into production.

• Support high-volume manufacturing and troubleshoot complex test issues.

AI Responsibilities

. Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements.

. Contributes to a culture of continuous improvement by identifying, testing, and sharing AI-enabled enhancements within one's scope of work.

Qualifications & Skills

• Education: Bachelor's or Master's degree in Electrical, Electronics or Computer Engineering.

• Experience: At least 3 years in Test Engineering with proven expertise in ATE Test.

• Technical Skills:

• Experience in ATE test program development, validation, and debugging

• Proficiency with Advantest V93K or similar ATE platforms

• Programming experience in Python, C/C++, or similar scripting languages

• Understanding of SoC testing concepts, with exposure to digital or memory test (e.g. MBIST, characterization)

• Familiarity with DFT concepts such as MBIST, SCAN, or pattern validation

• Exposure to test flow development, yield improvement, and failure analysis

• Experience working with high-volume manufacturing (HVM) environments

• Additional Knowledge:

• Understanding of semiconductor manufacturing processes.

• Experience with test data analysis tools (e.g. STDF, JMP, or similar)

• Familiarity with lab equipment and ATE debugging is a plus

• Soft Skills: Excellent communication, problem-solving, and collaboration abilities.

• Possess Micron Values: People, Innovation, Tenacity, Collaboration and Customer Focus