Sr Principal Design Engineer

Debugging, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, RTL changes for DFT, Zero delay and timing simulations, Post silicon bring up, Test architecture definition, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks

Debugging, Test Planning, Simulation, systemverilog, Uvm, IP verification, Testbench development, Verification architecture, Mentoring

testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog

static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

Coding, Usb, Verilog, Ethernet, Pcie, Sata, Rtl Design, RTL, ASIC Design, Principal