hardware engineering , Clock Tree Synthesis (CTS), Unix, Perl, Linux, Low power verification, floorplanning, Placement, power analysis, PNR implementation, CTS optimization, Optical systems, Equipment and packaging test systems, DSP systems

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus