G
Physical Design Engineer
G
- Posted 12 days ago
- Be among the first 30 applicants
Job Description
Description
We are seeking an experienced Physical Design Engineer to join our team in India. The ideal candidate will have a strong background in physical design implementation and will be responsible for optimizing IC layouts to meet performance and power requirements.
Responsibilities
- Perform physical design implementation of integrated circuits (ICs) from RTL to GDSII.
- Develop and optimize physical layouts for performance, power, and area.
- Conduct design rule checks (DRC) and layout versus schematic (LVS) verification.
- Collaborate with design engineers to resolve issues related to physical design.
- Utilize EDA tools for various stages of the physical design flow, including synthesis, place and route, and timing analysis.
- Engage in design reviews and provide feedback to ensure adherence to design specifications.
Skills and Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 6-15 years of experience in physical design engineering or a related field.
- Proficiency in using EDA tools such as Cadence, Synopsys, or Mentor Graphics.
- Strong understanding of VLSI design principles and physical design methodologies.
- Experience with RTL synthesis and timing closure techniques.
- Familiarity with scripting languages such as Tcl, Perl, or Python for automation.
- Excellent problem-solving skills and attention to detail.
- Ability to work collaboratively in a team environment.
Bachelor Of Technology (B.Tech/B.E), Masters in Technology (M.Tech/M.E)
More Info
Job Type:
Industry:
Role:
Function:
Employment Type:
Key Skills
About Company
Skills:
hardware engineering , Clock Tree Synthesis (CTS), Unix, Perl, Linux, Low power verification, floorplanning, Placement, power analysis, PNR implementation, CTS optimization, Optical systems, Equipment and packaging test systems, DSP systems
Skills:
Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog
Skills:
EM), Power integrity analysis (IR drop, Antenna), Physical verification (DRC, Static Timing Analysis (STA), Routing, Mentor Calibre, VLSI design principles, LVS, Physical design methodologies, floorplanning, Cadence Innovus, Synopsys Fusion Compiler, Semiconductor physics, Timing closure techniques, Design Verification, RTL synthesis, Placement, Deep sub-micron process technologies
Skills:
Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement
Skills:
power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation