bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, regression systems, congestion control, AI ML accelerators, systemverilog, vector processing units, digital systems, revision control systems, full verification life cycle, constrained-random verification environments, packet processing, Verification

C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, functional and code coverage closure

IP SoC verification, ASIC-SoC design verification, systemverilog

Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog

Perl, Shell scripting, Python, UVM Universal Verification Methodology, PCIe protocol, Debugging RTL and gate level simulation issues, systemverilog

Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts

Perl, Verilog, System Verilog, Python, Tcl, Mentor Questa, Cadence Xcelium, CHI, Ace, Synopsys VCS, Axi, AMBA, VHDL, RISC-V instruction set architecture, APB, UVM-based testbenches

Perl, Python, Tcl, ASIC design flow, LINT, Design Compiler, primetime, STA tools, UPF, Cadence Genus, RTL-to-gate-level synthesis, spyglass, CDC tools, CPF

Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification