Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts

Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm

Debugging, Automated Test Scripts, Documentation, Design Verification, Functional Verification, Test Plan Development

Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Python, Systemc, MDV, simulation scripts, hybrid testbenches, regression systems, verification execution, Uvm, systemverilog, testbenches, CDV, coverage models

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip