static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

C, Uart, Spi, Shell, Verilog, Ethernet, I2c, Python, Systemc, Tcl, SVI3, systemverilog, Axi, formal verification, DMA, UVM-based testbench development, AHB, power-aware verification UPF, NoC bus and interconnect verification

MBIST, Scan Insertion, ATPG, Debugging test pattern issues, LBIST, SRAM repair, DFT RTL insertion, Programming or scripting, DFT methodology, DFT implementation

redhawk , power integrity , Perl scripting, Debugging, Tcl, place-and-route, power network planning, system-level floorplanning, low-power design methodologies, Calibre, Innovus, VLSI logic design, Timing Closure, reliability EM IR analysis, Clock Tree Synthesis

arm architecture , C, Usb, DDR, Pcie, Perl, Ethernet, Tcl, hardware emulation support, TLMs in SystemC, Uvm, eMMC, assertion-based formal verification tools

Ovm, Tcl Scripting, Perl, Verilog, automation, Specman, SV, assertions development, functional and code coverages, RTL, Uvm, SDF sim debug, GLS, formal verification, eRM methodology, test-bench development, closure constraint randomization, HVL

Debugging, Clp, Silicon Validation, Dft, Scan Insertion, ATPG, Rtl Design, Timing Closure, LEC, IEEE 1500