C, Uart, Spi, Shell, Verilog, Ethernet, I2c, Python, Systemc, Tcl, SVI3, systemverilog, Axi, formal verification, DMA, UVM-based testbench development, AHB, power-aware verification UPF, NoC bus and interconnect verification

MBIST, Scan Insertion, ATPG, Debugging test pattern issues, LBIST, SRAM repair, DFT RTL insertion, Programming or scripting, DFT methodology, DFT implementation

static timing analysis, Dft, low-power design methodologies, LINT, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, formal verification, Logic Synthesis, cdc

arm architecture , C, Usb, DDR, Pcie, Perl, Ethernet, Tcl, hardware emulation support, TLMs in SystemC, Uvm, eMMC, assertion-based formal verification tools

Ovm, Tcl Scripting, Perl, Verilog, automation, Specman, SV, assertions development, functional and code coverages, RTL, Uvm, SDF sim debug, GLS, formal verification, eRM methodology, test-bench development, closure constraint randomization, HVL

Verilog, DDR, Test Planning, systemverilog, Uvm, Rtl Design, Functional Verification, LPDDR, HBM, Memory Subsystems, Verification Environment Development