Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

Perl, Verilog, Shell Scripting, LINT, cdc, RTL Quality Checks, Micro Architecture Definition, Connectivity, SOC design, VCLP

Python Scripting, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools

LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies

Perl, Verilog, Tcl, Python, VHDL, AXI Protocols, Ethernet protocol, Ethernet IPs, Rtl Design

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram

Verilog, Uvm, Synopsys VCS, VHDL, RTL design methodologies, Modelsim, Cadence Incisive